In recent years, attempts have been made to greatly improve the display quality of active matrix liquid crystal display devices. Many techniques have been proposed to solve problems such as image flicker and "image sticking" in which a fixed (still) image remains immediately after its display as if it had been burnt in. Flicker and burning-in, both of which deteriorate the display quality, are caused by a DC voltage component that unavoidably occurs in a display pixel due to anisotropy in the dielectric constant of a liquid crystal. In addition, techniques have been proposed for reducing the power consumption of active-matrix liquid crystal display devices to allow even a battery to drive them for a long time because the devices are used in a variety of portable apparatuses such as notebook-type computers.
A brief description will be made of the configuration of an active matrix liquid crystal display device that uses thin-film transistors (TFTs) as switching elements. To begin with, the liquid crystal is sealed between two glass substrates, i.e., an array substrate and an opposed substrate. A number of gate lines are formed on the array substrate horizontally, for instance, and a number of data lines are then formed thereon vertically over an insulating film. Pixel regions are formed with pixel electrodes in regions of the matrix sectioned by the gate lines and data lines. A TFT is formed in each pixel region, and a gate electrode and a drain electrode of the TFT is connected to the gate line and the data line, respectively. The TFTs source electrode is connected to a pixel electrode. The data lines are driven by a gate driving circuit and the data lines are driven by a data line driving circuit.
In an active matrix liquid crystal display, auxiliary capacitors are separately disposed because the liquid crystal pixel capacitance is small. The auxiliary capacitor is called a Cs-on-gate type in which a pixel electrode is laid on the gate line immediately preceding the gate line that is connected to the pixel concerned, and a storage capacitance type in which an independent wiring line (storage capacitance line) is formed.
FIG. 3 shows an equivalent circuit of display pixels of a liquid crystal display device in which additional capacitance type auxiliary capacitors are formed. Drain electrodes of TFTs 6 are connected to a plurality of data lines 4 attached to data line driving circuits (not shown). Gate electrodes of the TFTs 6 are connected to a plurality of gate lines 2 that are connected to gate line driving circuits (not shown). Source electrodes of the TFTs 6 are connected to respective display electrodes. The liquid crystal between the display electrodes on the array substrate and a common electrode on the opposed substrate constitutes the liquid crystal capacitances Cls 8. Part of each display electrode is laid on a gate line 2 of the immediately preceding scanline, to constitute an auxiliary capacitor Cs 10. A parasitic capacitance Cgs 12 exists between the gate and source of the TFT 6.
Recent active matrix liquid crystal display devices having the above configuration, have required that the display screen have higher resolution and the number of display pixels be increased. In association with these requirements, solutions have been proposed to various technical problems that have arisen. For example, Japanese Published Unexamined Patent Applications Nos. 2-157815 and 7-140441 disclose methods that can lower the degree of image flicker and the burning-in phenomenon, and also reduce power consumption. This is accomplished by compensating for a DC component that unavoidably occurs due to anisotrophy of a liquid crystal. However, these disclosed methods do not consider that the miniaturization of the gate lines, the increase in the number of wiring lines, and the increase of the wiring length, associated with improved resolution of the display screen and an increased number of display pixels, will increase the resistance of the gate lines and the load capacitance, and cause gate delaying. Nor do these disclosures solve the problem that gate delaying causes a variation in gradations and DC components having different levels in the horizontal direction of the display screen.
Gate delaying is considered an unavoidable problem in view of the improved resolution and the increased aperture ratio that are needed to increase the demand of liquid crystal display devices. For example, although gate delaying may be reduced by making the gate lines wider, that solution will decrease the aperture ratio of display pixels. As a result, to obtain given display brightness, the light intensity from a backlight needs to be increased, resulting in increased power consumption.
Further, in a method disclosed in Japanese Published Unexamined Patent Application No. 5-100636, a pixel voltage is written twice per frame to decrease a pixel potential variation caused by a reduced write period that results from improved resolution of the display. This method addresses the shortening of the gate on-time which results from the improved resolution of the display, but is not intended to solve the problem of a variation component (hereinafter called a feedthrough voltage) of the pixel potential which is caused by the parasitic capacitance between the gate and source of a TFT. Nor does this method consider that gate delaying causes different feedthrough voltages at various positions on the screen. Therefore, as in the case of the previously mentioned methods, this method reduces the aperture ratio of display pixels, resulting in increased power consumption.
Now, referring to FIGS. 4-7, a conventional liquid crystal driving method will be described in a more specific manner. The following explanation assumes a normally-black type liquid crystal display device in which the display brightness increases as the liquid crystal application voltage is increased. Drive waveforms shown in FIGS. 4 and 5 are adapted to compensate for both of a feedthrough voltage and an effective value. The effective value compensation means increasing the liquid crystal application voltage by adjusting a voltage applied to the auxiliary capacitor constituted by the gate line and the display electrode, even if the voltage level of gradation data supplied to the data line is decreased as a whole. The effective value compensation allows the liquid crystal to produce high brightness or receive a high voltage, even if the level of a voltage supplied to the data line is low. Since the level of a voltage supplied to the data line can be lowered, the power consumption of the liquid crystal display device can be reduced.
FIG. 4 shows a case where frame inversion driving is performed on a Cs-on-gate type liquid crystal display device. Parts (a) and (b) and part (c) respectively show input waveforms and a liquid crystal drive waveform on the side close to the gate line driving circuit, in which waveforms no gate delaying occurs.
When a gate signal (pulse width: 1 H (one horizontal scanning period) 22 is input to a gate line Gn+1 (see FIG. 4(b)), a TFT connected to this gate line is turned on, so that a voltage is applied to the liquid crystal as shown in FIG. 4(c). When the TFT is turned off, that is, at the fall of the gate signal 22, the feedthrough phenomenon causes the write voltage to the liquid crystal to decrease by a feedthrough voltage component 28 as shown in FIG. 4(c).
Thereafter (for instance, after a lapse of 0.5 H from the fall of the gate signal 22), feedthrough voltage compensation and effective value compensation 30 are effected as shown in FIG. 4(c) by causing a previous gate line Gn to have a potential Vc1 and applying a voltage to the auxiliary capacitor Cs. Further, final effective value compensation 32 is effected by supplying a signal of Vc1 to the gate line Gn+1 after a lapse of about 1 H from the rise of Vc1. As a result, the liquid crystal potential is set at Vlc(+) during frame 1.
Next, to AC-drive the liquid crystal in frame 2, feedthrough voltage compensation and effective value compensation are performed by a process similar to that in frame 1 at a voltage level Vc2 so that the liquid crystal potential becomes Vlc(-). As a result, a condition Vlc(+)=Vlc(-) is established, which enables liquid crystal display to be free of a DC component and be low in power consumption.
However, as described above, where gate delaying occurs, a gate signal assumes a waveform distortion as shown, for instance, in FIG. 6 at a position closer to a gate line terminal portion, so that the gate-off timing is delayed by .DELTA.t from 1 H. As a result, as shown in FIG. 5, the feedthrough amount decreases because a gate-source current flows for a longer time by an increased gate-on time than in the case of no gate delaying (FIG. 4). However, since the voltage levels Vc1 and Vc2 for the feedthrough voltage and effective value compensation do not vary, the liquid crystal potential becomes higher than a desired value (broken line in FIG. 5) in frame 1 and lower than that in frame 2. This causes a DC component Vdc (Vdc=Vlc(+)-Vlc(-)). That is, as shown in FIG. 7, while desired feedthrough/effective value compensation is effected for pixels closer to the gate line driving circuit (indicated as "supply side" in the figure), a DC component occurs for pixels closer to the gate line terminal portions so as to be larger at positions closer to the terminal portions.
In connection with the above problem, consideration is given to the case where drive waveforms as shown in FIG. 8 are used. In the drive waveforms of FIG. 8, the fall timing of a gate signal 22 that is input to a gate line Gn+1 is made coincident with a timing at which the potential level of a previous gate line Gn is raised to Vc1. In this case, even if the gate delaying causes the feedthrough voltage to be smaller at a position closer to a gate line terminal portion, it also makes the compensation potential Vc1 to appear smaller. Thus, the liquid crystal potential is prevented from having a DC component.
However, this driving method cannot provide sufficient effective value compensation for changing the amplitude of the liquid crystal potential, because the compensation voltage Vc1 appears smaller at a position closer to a gate line terminal portion. As shown in FIG. 9(c), although liquid crystal potentials V'lc(+) and V'lc(-) have no DC component (V'lc(+)=V'lc(-)), they are smaller than desired values Vlc(+) and Vlc(-), respectively.
As a result, as shown in FIG. 10, while desired feedthrough/effective value compensation can be effected for pixels closer to the gate line driving circuit (supply side pixels), the brightness decreases at pixels closer to the gate line terminal portions, causing unevenness in brightness over the entire display screen. As such, in either driving method, the gate delaying prevents the feedthrough voltage compensation and the effective value compensation from being effected at the same time. Therefore, it is impossible to lower the degrees of a flicker and the burning-in phenomenon and, at the same time, reduce the power consumption.
Therefore, an object of the subject invention is to provide a driving method of for active matrix liquid crystal display devices which method is superior in image quality and reliability and can reduce the power consumption even if the gate line load is increased as a result of increased size of a display screen, improved resolution, and an increased aperture ratio.